The trench capacitor is a well known capacitor design for use in integrated circuits (IC), especially in IC memory devices. While variations exist in particular designs, trench capacitors are generally characterized by the formation of a deep trench in the semiconductor substrate (wafer) typically normal to the principal plane of the substrate. Deeper and narrower trenches are generally more desirable in that they reduce the area in the principal plane occupied by the capacitor. The reduction of the planar area occupied by the capacitor allows capacitors and other devices forming the integrated circuit to be placed more closely together on the chip. More dense packing of the integrated circuit design may enable improved circuit designs and improved circuit performance.
The formation of trench capacitors and other trench-based devices typically involves selectively etching the substrate whereby a trench is formed in the substrate. The composition of the substrate in the vicinity of the trench and the composition components arranged in the trench are manipulated to form the desired capacitor or other trench device. Thus, for example, the substrate area immediately underlying the trench may be doped with a charge carrier species, portions of the trench may be lined with a dielectric material, the trench may be back filled with a charge storage material, etc.
In many instances, it is desirable to form layers on the substrate surface prior to forming the desired trenches in the surface. For example, one or more "pad" dielectric (oxide and/or nitride) layers may be applied to the substrate surface prior to formation of the trench. These dielectric layers are typically needed outside the trench as part of the ultimate circuit structure or as part of the overall circuit fabrication process.
General methods for forming trenches are well known. Typically, a TEOS (tetraethyl orthosilicate) hard mask is deposited over the dielectric layers by chemical vapor deposition. A photoresist layer applied over the TEOS layer and is patterned corresponding to the desired trench locations on the substrate. The substrate with the patterned photoresist is then etched where by trenches are formed in the substrate. The substrate is then subjected to further processing which may vary depending of the design of the integrated circuit, the desired performance level for the circuit, etc. Typically, the trenches will be used to form trench capacitors.
The trench formation method using a TEOS hard mask is widely used. See for example U.S. Pat. Nos. 5,656,535; 5,348,905; 5,362,663; 5,618,751 and 5,657,092, the disclosures of which are incorporated herein by reference. Unfortunately, the current process is problematic since it is difficult to remove the TEOS layer after trench formation (e.g. prior to formation of the buried plate) without adversely affecting existing oxide structures such as pad oxides. Thus, the removal of the TEOS layer must be delayed to a further point in the fabrication process. In the course of the delay, the underlying layers such as the pad nitride layer may be adversely affected (e.g. they may lose uniformity, etc.).